1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to alignment marks and die seal structures formed in the metallization system of semiconductor devices.
2. Description of the Related Art
Today's global market forces manufacturers of mass products to offer high quality products at a low price. It is thus important to improve yield and process efficiency and, thus, minimize production costs. This holds especially true in the field of semiconductor fabrication, since here it is essential to combine cutting edge technology with mass production techniques. It is, therefore, the goal of semiconductor manufacturers to reduce the consumption of raw materials and consumables while at the same time improve process tool utilization, since, in modern semiconductor facilities, equipment is required which is extremely cost intensive and represents the dominant part of the total production costs. Consequently, high tool utilization, in combination with a high product yield, i.e., with a high ratio of good devices to faulty devices, results in increased profitability.
Integrated circuits are typically manufactured in automated or semi-automated facilities, where the products pass through a large number of process and metrology steps prior to completing the devices. The number and the type of process steps and metrology steps a semiconductor device has to go through depends on the specifics of the semiconductor device to be fabricated. A usual process flow for an integrated circuit may include a plurality of photolithography steps to image a circuit pattern for a specific device layer into a resist layer, which is subsequently patterned to form a resist mask used in further processes for forming device features in the device layer under consideration by, for example, etch, implantation, deposition, polish and anneal processes and the like. Thus, layer after layer, a plurality of process steps are performed based on a specific lithographic mask set for the various layers of the specified device. For instance, a sophisticated CPU requires several hundred process steps, each of which has to be carried out within specified process margins so as to fulfill the specifications for the device under consideration.
For these reasons, a plurality of measurement data is typically obtained for controlling the production processes, such as lithography processes and the like, which may be accomplished by providing dedicated test structures, which are typically positioned within the actual die region or in an area outside of the actual die region. A corresponding outside the die region is also referred to as a frame region, which may be used for dicing the substrate when separating the individual die regions. During the complex manufacturing sequence for completing semiconductor devices, such as CPUs and the like, an immense amount of measurement data is created, for instance, by inspection tools and the like, due to the large number of complex manufacturing processes whose mutual dependencies may be difficult to assess so that usually factory targets are established for certain processes or sequences, wherein it is assumed that these target values may provide process windows so as to obtain a desired final electrical behavior of the completed devices. That is, the complex individual processes or related sequences may be monitored and controlled on the basis of respective inline measurement data such that the corresponding process results are held within the specified process margins, which in turn are determined on the basis of the final electrical performance of the product under consideration. Consequently, in view of enhanced overall process control and appropriately targeting the various processes on the basis of the final electrical performance, optical inspection data obtained from within the die regions and also electrical measurement data is created on the basis of the dedicated test structures provided in the frame region.
In sophisticated semiconductor devices, not only the circuit elements formed in and above a corresponding semiconductor layer require thorough monitoring, but also the metallization system of the semiconductor device is of high complexity, thereby also requiring sophisticated process and material monitoring techniques. Due to the ongoing shrinkage of critical dimensions of the semiconductor-based circuit features, such as transistors and the like, the device features in the metallization system also have to be continuously enhanced with respect to critical dimensions and electrical performance. For example, due to the increased packing density in the device level, the electrical connections of the circuit elements, such as the transistors and the like, require a plurality of stacked metallization layers, which may include metal lines and corresponding vias, in order to provide the complex wiring system of the semiconductor device under consideration. Providing a moderately high number of stacked metallization layers is associated with a plurality of process-related challenges, thereby requiring efficient monitoring and control strategies. For instance, in sophisticated applications, electrical performance in the metallization systems is typically increased by using dielectric materials having a low dielectric constant in combination with metals of high conductivity, such as copper, copper alloys and the like. Since the manufacturing process for forming metallization systems on the basis of dielectric materials of reduced permittivity, also referred to as low-k dielectrics, and highly conductive metals, such as copper, may include a plurality of very complex manufacturing steps, a continual verification of the process results is typically required in order to monitor the overall electrical performance of the metallization system and also performance of associated manufacturing strategies.
Measurement processes to be performed on semiconductor devices during the various phases of the production process are typically performed on the basis of automated measurement systems, in which appropriate alignment mechanisms are implemented in order to appropriately adjust the measurement site with respect to the actual die region or frame region. For example, many optical inspection techniques, such as elipsometry, scatterometry and the like, may critically depend on automated alignment procedures so as to identify appropriate areas within a die region or to identify respective test structures. To this end, typically, appropriate alignment marks are positioned at or in the vicinity of the corners of the die region, which have a characteristic shape, such as a cross-shaped configuration, which may be efficiently identified by the alignment mechanism of the inspection tool or measurement tool under consideration. In this manner, the actual inspection field or measurement field provided by the measurement tool under consideration may be appropriately positioned with respect to the alignment mark, wherein usually a certain lateral distance between the alignment mark and the actual measurement field accessible by the measurement tool is to be taken into consideration. Consequently, in many cases, the actual measurement site may be desirably selected as large as possible in order to have the ability to inspect or measure the entire die region, or at least a very large fraction thereof.
As discussed above, typically, the semiconductor die regions are provided in an array form on an appropriate substrate, wherein the frame regions may provide appropriate lateral offsets of the individual die regions in order to enable appropriate dicing of the substrate upon separating the individual die regions. The width of these scribe lines, on the other hand, may be desirably reduced in order to not unduly waste valuable chip area. On the other hand, the process of dicing the substrate may have a significant influence on the die regions due to the mechanical interaction of a diamond saw blade on dicing the substrate. For this reason, typically, a die seal is provided at the periphery of the actual die regions in order to provide a mechanical “barrier” that should avoid or at least significantly reduce the effects of the mechanical influence during the dicing process. In particular, in combination with highly sophisticated metallization systems, the mechanical barrier effect of the die seal is of great importance, since, typically, low-k dielectric materials and ULK (ultra low-k) materials, which are increasingly used in complex metallization systems, may have a reduced mechanical strength compared to conventional dielectric materials, such as silicon nitride, silicon dioxide and the like. The die seal may thus be provided in the form of appropriate metal features, which may form an appropriate network so as to be firmly connected and embedded in the dielectric material and which may appropriately extend through the metallization layers down into the semiconductor material so as to provide sufficient mechanical strength at the periphery of the die regions. In order to provide the required mechanical characteristics, typically, a certain “metal density” has to be provided within the die seal region and also a certain width of this region may be necessary when appropriate mechanical integrity of the die region is to be ensured.
It turns out, however, that the provision of a mechanically stable die seal and alignment marks, which may allow superior accessibility of the actual die region, may not be compatible with conventional designs and strategies, as will be described in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a top view of a portion of a semiconductor substrate having formed thereon a plurality of semiconductor die regions 100, such as die regions 100A, 100B, 100C. As indicated, these die regions are provided in an array form with an appropriate lateral spacing in between, which may be indicated as frame regions or as scribe lines 151y, 151x. It should be appreciated that, for convenience, the lateral dimensions of the die regions 100 and of the frame regions 151y, 151x are not true to scale. Furthermore, each of the die regions may comprise a die seal region 120, which is to be understood as the area at the periphery of each die region 100, in which a certain density of metal features is to be provided in each metallization layer of a metallization system formed above the substrate. Thus, the die seal regions 120 surround actual inner die regions or “active” regions 110 in which the actual circuit elements and possibly any test structures are to be provided. It should be appreciated, however, that also any test structures (not shown) may be provided within the frame region 151y, 151x if the test results obtained thereof are considered appropriate for estimating characteristics of actual inner die regions 110 and respective manufacturing processes. Furthermore, as shown, one or more alignment marks 130 are typically provided, for instance as a cross, and having appropriate lateral dimensions so as to be readily recognizable by automated alignment mechanisms of inspection tools, or generally measurement and process tools and the like.
FIG. 1b schematically illustrates a more detailed view of a portion of a die region 100. As shown, the die seal region 120 may comprise a plurality of appropriate metal features 122, such as metal line portions, vias and the like, as considered appropriate for achieving the desired high metal density and enable mechanically stable connection to any lower-lying and over-lying further metallization layers. As shown, the die seal region 120 may comprise an outer boundary 1200 and an inner boundary 1201, which define the effective width 120W of the die seal region 120. It should be appreciated that, typically, the boundaries 1200, 1201 may be defined on the basis of layout criteria, such as the presence of non-functional metal features and the like. Typically, the width 120W may be substantially equal at any position around the entire die seal region 120. Moreover, the alignment mark 130 is positioned closely to the die seal region 120, i.e., a corner area thereof. Consequently, upon performing an automated alignment process, typically, a certain lateral offset 110D of the actual inspection field or measurement field 110A provided by the measurement tool under consideration is required with respect to the position of the alignment mark 130. In this case, the peripheral area of the actual inner die region 110 is thus outside of the actual measurement field 110A and is thus not accessible for the measurement or inspection process of interest. For this reason, it has been proposed the alignment mark be outside of the inner die region 110 which, however, may unduly affect the configuration of the scribe lines, i.e., typically an increased width would be required and/or a reconfiguration of corresponding test structures and the like may be necessary.
FIG. 1c schematically illustrates a top view of the portion of the die region 100 according to further alternative suggestions in which the alignment mark 130 is “integrated” into the die seal region 120. Consequently, the actual inspection field 110A may be positioned more closely to the die seal region 120, thereby enabling the measurement of an enlarged area within the die region 110, wherein, however, a significantly reduced width 120R of the die seal region 120 and thus a significantly reduced mechanical strength is obtained. Consequently, upon dicing the substrate, significant mechanical damage may be caused unless the corresponding scribe lines are increased in width, thereby significantly reducing the overall process throughput.
In view of the situation described above, the present disclosure relates to semiconductor devices in which alignment marks may be positioned in a space-efficient manner, while avoiding, or at least reducing, the effects of one or more of the problems identified above.